Technological Field
The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers.
Description of the Related Technology
Direct bonding on wafer level, commonly referred to as ‘wafer-to-wafer’ bonding, involves the alignment and contacting at room temperature of two semiconductor wafers, e.g., silicon wafers, followed by an annealing step, during which step chemical bonds are formed between the materials on at least a portion of the contacted wafer surfaces.
Wafer-to-wafer bonding technologies fall under two main categories. In a first category, surfaces of both wafers are blanket, or flat unpatterned dielectric bonding layers. The bonding layers can be formed of, e.g., silicon oxide, silicon nitride or a low-k dielectric layer (e.g., silicon-carbon-oxide layer). In a second category, sometimes referred to as hybrid wafer bonding, the surfaces of both wafers are flat and patterned dielectric/metal layers. The main area fraction of the surface of each wafers is covered by the dielectric material, while other areas are metallic, mainly forming contact pads and metal lines. Bonding between dielectric areas takes place by the same mechanism as described above with respect to the first category. Locations where metallic areas overlap can be used to realize electrical contacts between the wafers.
For both categories, the challenge is to achieve a very flat, low roughness dielectric bonding layer which is beneficial for obtaining void-free bonds with a high bond strength. In some technologies, chemical mechanical polishing (CMP) is applied to reduce the roughness of the dielectric layers. In some technologies, surface treatments are applied, e.g., plasma surface treatment and ultrasonic or other cleaning techniques. Post-bond annealing is generally performed at temperatures higher than 400° C. in order to reach the desired bond strength. In order to reduce the thermal budget of the bonding process, it is desirable to obtain high strength bonds at lower temperatures. This can be particularly important in the field of memory devices, where the substrates have formed or partially formed thereon memory device structures, which can degrade at high temperatures.
For the second category, an additional problem is the diffusion of the metal into the dielectric bonding layer. This is the case for example when silicon oxide bonding is applied to bonding of hybrid wafers that comprise copper line patterns, resulting in direct Cu contact to the oxide surface of the mating wafer. During annealing, the Cu may diffuse in the oxide, resulting in leakage or shorting between interconnect nets. In order to avoid this diffusion, a dielectric bonding layer can be applied that forms a barrier against the Cu-diffusion, such as silicon nitride. However, this makes achieving a high bonding force more difficult and increases the interconnect capacitance due to the higher dielectric constant of the Si nitride versus the Si oxide.
The same problems are confronted in the ‘die to wafer’ bonding processes, wherein a silicon chip is bonded to a carrier wafer by direct bonding. In the latter domain, it has been known to apply Silicon Carbon Nitride (SiCN) as the dielectric bonding layer. Reference is made to US2013/0207268. Like silicon nitride, SiCN is a good Cu diffusion barrier. However, the cited document fails to describe the bonding process in detail and no information is given on applicable annealing temperatures. US2010/0211849 describes SiCN as a ‘bonding aid film’ in a direct wafer-to-wafer bonding process. This process is however open to further improvement in terms of the thermal budget (the post-bonding annealing temperature is 400° C.).